ISO 11898-5 PDF

A Controller Area Network CAN bus is a robust vehicle bus standard designed to allow microcontrollers and devices to communicate with each other's applications without a host computer. It is a message-based protocol , designed originally for multiplex electrical wiring within automobiles to save on copper, but can also be used in many other contexts. For each device the data in a frame is transmitted sequentially but in such a way that if more than one device transmits at the same time the highest priority device is able to continue while the others back off. Frames are received by all devices, including by the transmitting device.

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Unless otherwise specified, no part of this publication may be reproduced or utilized in any form or by any means, electronic or mechanical, including photocopying and microfilm, without permission in writing from either ISO at the address below or ISO's member body in the country of the requester. ISO — All rights reserved Bibliography The work of preparing International Standards is normally carried out through ISO technical committees.

Each member body interested in a subject for which a technical committee has been established has the right to be represented on that committee.

International organizations, governmental and non-governmental, in liaison with ISO, also take part in the work. The main task of technical committees is to prepare International Standards. Draft International Standards adopted by the technical committees are circulated to the member bodies for voting.

Attention is drawn to the possibility that some of the elements of this document may be the subject of patent rights. ISO shall not be held responsible for identifying any or all such patent rights. Part 1: Data link layer and physical signalling Part 2: High-speed medium access unit Part 3: Low-speed, fault-tolerant, medium-dependent interface Part 4: Time-triggered communication. It covered the CAN data link layer as well as the high-speed physical layer.

In the reviewed and restructured ISO series:? Part 2 defines the high-speed medium access unit MAU ; Part 3 defines the low-speed fault-tolerant medium access unit MAU ; Part 4 defines the time-triggered communication; Part 5 defines the power modes of the high-speed medium access unit MAU. Part 1 describes the data link layer including the logical link control LLC sub layer and the medium access control MAC sub layer as well as the physical signalling PLS sub layer;.

This part of ISO represents an extension of ISO , dealing with new functionality for systems requiring low-power consumption features while there is no active bus communication. Physical layer implementations according to this part of ISO are compliant with all parameters of ISO , but are defined differently within this part of ISO Implementations according to this part of ISO and ISO are interoperable and can be used at the same time within one network.

For dated references, only the edition cited applies. For undated references, the latest edition of the referenced document including any amendments applies. ISO , Road vehicles — Electrical disturbances from conduction and coupling — Part 3: Electrical transient transmission by capacitive and inductive coupling via lines other than supply lines ISO , Road vehicles — Controller area network CAN — Part 2: High-speed medium access unit.

ISO — All rights reserved For the purposes of this document, the terms and definitions given in ISO and the following apply. CAN node? The values of the voltage levels, the resistances and the capacitances as well as the termination network are described in Clause 7. These terminations are intended to suppress reflections.

Besides this reflection-optimized termination structure, centralized single terminations are possible at limited bit rates and topologies. ISO — All rights reserved 3. Key 1 physical layer In order to support low-power functionality, two different modes of operation are defined as follows.

Normal mode: The behaviour during normal mode is described within ISO Low-power mode: Described within this part of ISO Bus levels during normal mode 5.

ISO — All rights reserved The bus can have one of the two logical states: recessive or dominant see Figure 3. The bus is in the recessive state if the bus drivers of all CAN nodes are switched off.

Vdiff is less than a maximum threshold. The recessive state is transmitted during bus idle or a recessive bit. Figure 3 illustrates the maximum allowed differential recessive bus voltage. Typically, the differential voltage is about zero volts. Optionally the recessive bus state may become stabilized making use of a dedicated split termination voltage VSplit. This optional output voltage of physical layer implementations according to this part of ISO may be optionally connected to the centre tap of the split termination resistors.

Whenever the receiver of a physical layer is not actively biasing towards 2,5 V, the optional VSplit shall become floating.

A dominant bit is sent to the bus if the bus driver of at least one unit is switched on. This induces a current flow through the terminating resistors, and consequently a differential voltage between the two wires of the bus. A differential voltage greater than a minimum threshold represents the dominant state. The dominant state overwrites the recessive state, and is transmitted during a dominant bit.

The dominant and recessive states are detected by transforming the differential voltages of the bus to the corresponding recessive and dominant voltage levels within the receive comparator. During arbitration, various CAN nodes may simultaneously transmit a dominant bit. In this case, Vdiff exceeds the Vdiff seen during a single operation. Single operations means that the bus is driven by one CAN node only.

It is not possible to actively drive a differential level to the bus lines using a physical layer within low-power mode. In contrast to the normal mode behaviour, the bus wires shall be pulled to the ground signal of the module GND via the high-ohmic internal input resistors Rin of the receiver. Thus, there is no active VCC supply required defining the bus levels during lowpower operation.

The optional split termination voltage VSplit is disabled here and shall behave high-ohmic floating in order not to pull the bus into a certain direction.

From a physical point of view, there are only the two defined operating conditions possible. Key 1 2 3 normal mode low-power mode simplified transceiver bias implementation. Implementations supporting this feature shall make use of a differential bus comparator monitoring the bus line.

A bus wake-up shall be performed if the bus shows one or multiple consecutive dominant bus levels for at least tWake, each separated by a recessive bus level. In order to allow undisturbed CAN communication in systems, which have a couple of nodes intentionally unpowered e. This requires that transceivers, which are temporarily unpowered, show a lowest possible leakage current to the bus lines inside the still communicating system. The lower the leakage current in the unpowered case, the better the system performance in the permanently supplied part of the network.

Depending on the target application permanently supplied or temporarily unsupplied the maximum leakage parameter according to Table 4 can be tolerated permanently supplied nodes or should be reduced as far as possible temporarily unsupplied nodes.

Besides these tests, some tests are added dealing with the optional VSplit functionality and the low-power mode behaviour. When this function is implemented, the behaviour of that output shall be measured as shown within the following clauses.

In unloaded condition Figure 4 schematic C , the output voltage shall be checked according to Table 6 using a load resistance of W 1 M?.

The leakage current is defined in Table 6. Applying a voltage UTest to the test circuit allows the calculation of Rin based on the voltage divider defined with RTest as follows: 6 fx Figure 7 — Measurement of Rin during low-power mode w? Figure 8 — Measurement of tProp during normal mode 6. Dominant pulses with a length between tWake min and tWake max may lead to a wake-up depending on filter spread.

According to the target bit rate of the system, the individual time thresholds of an implementation can be adapted, but shall stay within the defined minimum and maximum timings as defined in Table The test shall be performed within the full common mode voltage range as specified in Table 3.

An oscilloscope is used to verify that the so-called common mode bus voltage stays within the limits during the recessive bit time, the dominant bit time and the bit transition times, according to Table 5. See Figure Figure 11 — Measurement of input leakage current of an unpowered device 7 7. All data given in Tables 1 to 10 are independent of a specific physical layer implementation. The parameters specified in these tables shall be fulfilled throughout the operating temperature range as specified for every individual CAN node.

The parameters specified in Tables 1 to 6 apply when all CAN nodes are connected to a correctly terminated bus. The bus load increases as CAN nodes are added to the network, by Rdiff. Consequently, Vdiff decreases. The minimum value of Vdiff determines the number of CAN nodes allowed on the bus.

The maximum value of Vdiff is specified by the upper limit during arbitration. ISO — All rights reserved a The differential bus voltage is determined by the output behaviour of all CAN nodes during the low-power mode. Therefore Vdiff is approximately zero see Table 8.

Therefore, Vdiff is approximately zero see Table 8. Input leakage current a Value nom. A leakage of less than 25? A is recommended for devices which are intended to be used in unpowered condition while permanently supplied nodes might benefit from the full specified leakage range. In case of multiple supply inputs provided by the implementation, all supply inputs shall carry 0 V with respect to GND. A — 0 Split leakage current, low-power mode 7. Condition —? There is no destruction of bus driver circuit and no time limit.

Range for receiving a recessive bit. Differential internal resistance Internal resistor b a b Value nom. Reception shall be ensured within the common mode voltage range specified in Table 1 and Table 2 respectively.

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